The present invention relates to a field memory device which is essential to enhanced density televisions (ED-TV) and high definition televisions (HD-TV) and, more particularly, to a video field memory device for multiple TV broadcasting systems for varying a desired scanning bit or a desired scanning line inside a single chip by using external signals for selecting one of TV broadcasting systems independent of the scanning bit or the scanning line which is different according to each television broadcasting system, and a processing method therefor.
In a conventional video field memory and frame memory for processing a digitalized video signal, there is a restriction that the memory devices must be selected differently depending on the television broadcasting system. The NTSC system and the PAL system have different scanning bits and lines.
Also, in the digital selection broadcasting system to be generalized at the next generation, the video field memory temporarily stores a constant image scene provided through a tuner and converts it to a digital signal. Thus, the video field memory has to input or output a video data signal at a high speed by a special function, and the structure and the density of video memory cells are different from each other because the video field memory is used for a video display.
FIG. 1 shows a block diagram of the conventional video field memory device, comprising upper and lower half memory cell arrays 11 and 13 corresponding to the scanning bit and the scanning line of the NTSC and PAL systems, write data registers 8 and 9 for writing serial input data in parallel through a data input buffer 10 at a line of the upper and lower memory cells, data write pointers 6 and 7 for assigning write bit points to the write data registers 8 and 9, data read registers 15 and 16 for reading the output parallel data in serial at a line of the upper and lower half memory cell arrays 11 and 13, data read pointers 17 and 18 for assigning read bit points to the data read registers 15 and 16, a line address decoder 5 for decoding the read and write address lines of the upper and lower half memory cell arrays 11 and 13 according to the sequences of the address pointers assigned among a read address pointer 2, a write address pointer 3 and a refresh address pointer 4, a timing generator 1 for controlling the timing sequence of each of the address pointers 2, 3 and 4 by being driven according to a control signal .phi. and a refresh signal provided from a refresh timing generator 20, and a data address output buffer 19 for providing a read data output DOUT from the data read register 16 in serial.
Also, the timing sequence and the signal from the time pointer are transmitted between the timing generator 1 and the data read registers 15 and 16.
In the conventional video field memory device, a write data input DIN is applied to the data input buffer 10 and the buffered write data is serially transmitted to the write data registers 8 and 9 respectively. Subsequently, the serially transmitted write data is transmitted in parallel and are written to the upper and lower half memory cell arrays 11 and 13 respectively according to the pointing sequences of the write data pointers 6 and 7, respectively. Next, the written data is serially provided to the data read registers 15 and 16 from the memory cell array 11 and 13 and applied to the data read output buffer 19 in parallel. Then, the read data output DOUT is provided from the read address output buffer 19 in sequence of the addresses according to the pointing sequences of the lines assigned by the address read pointers 17 and 18.
Under this condition, the timing generator 1 controls a corresponding one among the read address pointer 2, the write address pointer 3, and the refresh address pointer 4 in response to the fixed scanning bit and line of the memory cell arrays 11 and 13. Further, the address of the address pointers 2, 3, or 4 is provided to the line address decoder 5, thereby decoding the memory cell arrays 11 and 13 in unit of block.
In the conventional video field memory device, the memory cell arrays and their peripheral circuits are designed to be suitable only for a particular television system, for example, the NTSC or PAL system, so that, for the multi-broadcasting system television, they have to be changed differently.
Up to now, digital multi-broadcasting system televisions for processing the digital video signal, also, have to employ differently designed field or frame memory depending on the broadcasting system.